View YGV627-V_3751859.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ygv627 catalog catalog no.: lsi-4gv627a60 2005.1 ygv627 avdp3e advanced video display processor 3 enhanced outline ygv627 is a vdp (video display processor) that realizes higher resolution, multi-color and high speed drawing by adopting a synchronous dram as the video memory, while maintaining the register compatibility with ygv617b that is used for controlling the high minuteness on screen display (osd). since the device is capable of displaying bitmap images with various resolutions ranging from ntsc to svga on the monitors with any size of screen including wide screen, it can be used for controlling osd for various display units. also, it is capable of representation of va ried images in accordance w ith the application because numerous number of colors can be selected such as the one in the range from 16 to 65536 rgb color display, or natural image display using ycrcb. in addition, the existing system can be up-graded easily thanks to the basic features from ygv617b such as a high speed drawing function, character drawing function, synchronization with external video signal, digital video input / output function, and hardware cursor display function. features ygv627 is capable of selecting tw o modes by using the setting of enh pin. for convenience, the case of using enh pin with low level (enabled) is referred to as ?expansion mode? in this document. in the expansion mode, all the functions can be used. the case of using enh pin with high level (disabled) is referred to as ?compatibility mode?. in the compatibility mode, the software compatibility with yg v617b is maintained, but the functions enhanced for ygv617b cannot be used. these modes should be used in accordance with the purpose of the application of this device. [display functions] z three screen configuration including bitmap screen, sprite cursor screen and external input video screen (or single color border screen) z monitor synchronization frequency, dot clock frequency, and display screen resolution can be specified optionally. z display dot clock up to 40 mhz (example of resolution: ntsc, pal, vga, svga, ntsc wide, and vga wide) z support with progressive scanning and interlaced scanning z resolution of sprite cursor screen is 32 x 32 dots. (the sprite cursor can also be used as cross-hair line cursor.) z smooth hardware scroll function z upper / lower two division display on the bitmap screen (the two sections can be scrolled independently). z 256 words x 16 bits clut is built-in (the number of display colors of 32768 colors or 65536 colors can be selected.) z display colors: 16 palette color, 256 palette color, 32768 rgb color, 65536 rgb color, ycrcb422 (itu601) z ycrcb(itu601) -to-8 bit rgb decoder is built-in. z blending function that mixes with external input screen or single color border screen. (64 intensity levels) z dot clock generation with built-in pll circuit z generates dot clock that synchronizes with hsync of external video signal. z generates dot clock that synchronizes with exte rnal input clock. (such as sub-carrier clock)
ygv627 2 [drawing functions] z commands block transfer by word (cpu to vram, vram to cpu, vram to vram) font drawing, dot drawing and rectangular drawing. z drawing attribute sets drawing clip area, drawing offset or drawing page, and designates bit mask, color mask, logical operation (not, and, or, eor etc.), or direction of transfer. [operational clock] z system clock (clock for drawing system): up to 33 mhz z dot clock (clock for display system): up to 40 mhz [cpu interface] z 16 bit or 8 bit asynchronous interface z provided with a video memory space up to 8m bytes and internal register space of 128 bytes. z the video memory space and internal register space can be mapped indirectly with 16 byte registers. z built-in data buffer for memory space access and built-in data fifo for drawing commands z cpu interruption based on various conditions of display and drawing z dma transfer of drawing command data can be made when connected with external dma controller [video memory interface] z connected memory: 16m bits sdram (512k words x 16 bits x 2 banks) 1 piece or 64m bits sdram (1m words x 16 bits x 4 banks) 1 piece z sdram clock: up to 66 mhz (system clock multiplied by 2 or 4) z built-in fifo for display data improves the drawing access efficiency and realizes high speed drawing. [monitor interface] z analog rgb output with built-in dac (8 bits for rgb individually) z digital video input / output (6 bits for rgb individually) z equipped with sub-carrier clock output, dot clock output, sync signal output, ys and attribute output pins. [others] z package: 176lqfp (YGV627-V) z cmos, 3.3v single power supply z operating temperature range: ? 40 to +85 c supplementary information: for ygv627, application manual that details the specifications of the device and the evaluation board (msy627db01/02) are available in addition to this brochure. the evaluation board is equipped with an sdram of 8 mb as a video memory. a high performance system can be realized when it is used with hitachi?s cpu board, super h solution engine. the device driver provided by yamaha and attached to the evaluation board consists of the main body of the driver and api related layers, allowing the user to build it into the system eas ily according to the environment. for the details of these products, inquire of the sales agents or our business offices. for cpu board, inquire of: hitachi ulsi systems co., ltd. tel:+81-42-351-6600
ygv627 3 block diagram drawing command cpu memory control sync. control pll displa y control screen synthesis digital video input a nalog rgb ygv627 osd screen cpu interface sdram 16mbit 16 16 tft panel digital video output (also used as digital video input pin) dac internal block diagram ygv627 is connected to the external memory bus of cpu as an external i/o device. as a video memory, sdram of up to 64m bits can be connected to local memory bus of ygv627 to send bitmap image data stored in the video memory into monitor as rgb signal in accordance with display scan timing. ygv627 stores image data from cpu to the video memory by accessing video memory directly through cpu interface or by accessing the video memory using internal drawing command that transfers the data by block. ygv627 has a function that synthesizes external images with bitmap image of ygv627 on the screen by synchronizing the scan timing of ygv627 with display timing of external video signals.
ygv627 4 pin assignment top view cas nc vdd vss vss vdd vd2 vd14 vd1 vd15 vd0 vd6 vdd vd10 vd5 vd11 vd4 vd12 vss vd3 vd13 ba0 dqmh dqml vd8 vss vd7 vd9 vdd sdclk vss ba1 va11 va0 va8 va10 va9 nc va1 va7 vss vdd vss vss vdd va4 va3 va5 va2 va6 nc dotclk dv6 dv5 dv4 dv3 dv2 dv1 dv0 dv15 dv14 dv13 dv12 vdd dv11 dv10 dv9 dv8 vss dv7 vdd at ys fsc vss dv17 dv16 nc vss nc vss vdd syckin syckout dtckin dtckout avdd2 dpllfilt dpllrref dpllvssr avss2 avss3 r g b iref avdd3 lwd a0/ avdd1 spllfilt spllrref spllvssr avss1 nc a4 a3 a2 a1 nc a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a21 a20 a19 a18 a17 a16 a15 d0 vdd vss a22 d13 d12 d11 d10 d9 d8 vss d7 d6 d5 d4 d3 d2 nc d15 d14 d1 1 11 10 9 8 7 6 5 4 3 2 21 20 19 18 17 16 15 14 13 12 28 27 26 25 24 23 22 34 33 32 31 30 29 42 41 40 39 38 37 36 35 44 43 45 55 54 53 52 51 50 49 48 47 46 65 64 63 62 61 60 59 58 57 56 72 71 70 69 68 67 66 78 77 76 75 74 73 86 85 84 83 82 81 80 79 88 87 132 122 123 124 125 126 127 128 129 130 131 112 113 114 115 116 117 118 119 120 121 105 106 107 108 109 110 111 99 100 101 102 103 104 91 92 93 94 95 96 97 98 89 90 176 166 167 168 169 170 171 172 173 174 175 156 157 158 159 160 161 162 163 164 165 149 150 151 152 153 154 155 143 144 145 146 147 148 135 136 137 138 139 140 141 142 133 134 ready dreq wait int int2 we ras cs blank hsync vsync csync hsin vsin dvout enh test2 test1 test0 sysel rd wr0 dmap reset csreg csmem dack vr64 wr1
ygv627 5 pin functions d15 ? 0 ( i/o: pull up ) this is a data bus for connecting with external processor. d15 ? d8 are not used when the cpu bus with 8 bit type (when low level is inputted to lwd). at this time, keep the d15 ? d8 open. these pins are provided with pull-up resistors respectively. a22 ? 1 ( i ) this is an address bus to be connected with external general purpose microcomputer. in the indirect access mode (high level inputted to dmap pin), input to a22 ? a4 pins are ignored when accessing csreg space. in the direct access mode (low level inputted to dmap pin), input to a22 ? a8 pins are ignored when accessing csreg space. ygv627 can be used as a ygv617b compatible device when a22 and a21 pins are fixed to low level. unused pins must be set to low level or high level. csreg ( i ) it is a chip select signal input to register space (i/o). when this chip select signal is active, the read / write pulses inputted are made valid so that the registers in the ygv627 are accessed. the function of this pin is the same as that of csio pin of ygv617b. csmem ( i ) this is a chip select signal input pin for video memory port. the read / write pulse inputted while this signal is active can be used to directly access the video memory controlled by ygv627. it is possible not to use csmem because the video memory can also be accessed from registers. in such case, it is necessary to input high level to csmem pin. a0 / wr1 , wr0 ( i ) when chip select input is active, these pins control write access to ygv627. d15 ? d8 are controlled by a0 / wr1 , and d7 ? d0 by wr0 . when the cpu is 8 bit type, a0 / wr1 functions as cpu address bit 0. rd ( i ) when chip select input is active, rd controls read access from ygv627. d15 ? d0 are in output state in the period while both this signal and chip select signals are active. ready ( o: pull up, 3-state output ) this is data ready signal output to cpu. the read y signal is made low when the internal state of ygv627 is accessible. read y is a 3-state output. when csreg or csmem is not active, it is high impedance state, and when csreg or csmem is active and rd or wr1 , wr0 is not active, high level is outputted from read y . some cpu must use wait signal instead of this signal. a22-a1 csreg, csmem a0/wr1, wr0 d15-0 (input) ready valid valid hi-z hi-z ready signal at write access
ygv627 6 wait ( o: pull up, 3-state output ) this is data wait signal output to cpu. when csreg or csmem is active, the level of wait signal is made low once with respect to rd or wr1 , wr0 in accordance with the internal state of ygv627, and in accessible state, it outputs high level. when csreg or csmem is not active, it is in high impedance state, and when csreg or csmem is active and rd or wr1 , wr0 is not active, high level is outputted from this pin. some cpu must use read y signal instead of this signal. a22-a1 a0/wr1, wr0 d15-0 (input) wait valid valid hi-z hi-z csreg, csmem wait signal at write access int ( o: open drain output ) this is interrupt request signal output to cpu. this signal is made low when the internal state of ygv627 coincides with the setting conditions of registers. this signal is reset with access to ygv627?s internal register. int2 ( o: high speed bus interrupt output ) this is an interrupt request signal output to cpu, and its output logical value is the same as that of int . for high speed cpu bus, this output signal is used to avoid the influence of transit time caused by the pull-up resistor when the interrupt signal is negated. use int or int2 in accordance with the requirement of the system into which the ygv627 is built-in. lwd ( i: pull up ) this is used to select width of cpu data bus. when this signal is high level input, the device is compatible with 16 bit system and when low level input, the device is compatible with 8 bit system respectively. since lwd is used for selection of a mode, always fix it to either level. reset ( i: pull up, with schmitt ) initial reset signal is inputted to reset . the reset signal input resets the internal state of the device and the internal registers are cleared to ?0?. (som e registers are loaded with initial value.) be sure to input the reset signal after power up. dreq ( o ) dreq outputs command data request signal to external dma controller. dack ( i: pull up ) command data transfer permission signal is inputted to dac k in response to dreq signal to external dma controller. dmap ( i: pull up ) dmap is used to select a register space mapping method. when high level is inputted, 16 byte indirect mapping is selected. when low level is inputted, all the registers except clut are mapped directly in the 128 byte space. the input to dmap determines the valid address when csreg signal is active. dmap input signal is valid regardless of the state of enh input signal. when using ygv627 in ygv617b compatibility mode, input high level to dmap . since dmap is for selection of a mode, always fix it to either level.
ygv627 7 enh ( i: pull up ) this signal permits enhanced functions for ygv617b. when high level is inputted, only the registers that are compatible with ygv617b are made valid, and the function of the enhanced registers are fixed to their default values. when low level is inputted, the function of the enhanced register is made valid. this pin selects enable / disable of the enhanced functions and determines sdram access timing at the same time. in compatibility mode, the timing of access to sdram is equal to that of the performance of ygv617b, but in enhancement mode, the access performance is doubled. since enh is for selection of a mode, always fix it to either level. < video memory interface> ba1 ? 0, va11 ? va0 ( o ) these pins output address for sdram that is used as a video memory controlled by ygv627. they output row address and column address on time sh aring basis. ba1 and ba0 output bank address. however, when v r64 is a high level input (16m bits sdram is connected), va11 becomes bank select. when a read command or write command is sent to the sdram, va10 functions as auto-precharge enable. since these pins are always driven by ygv627, vram halt function of ygv617b cannot be used. vd15 ? vd0 ( i/o: pull up ) these pins constitute a data bus for sdram that is used as video memory controlled by ygv627. vram halt function of ygv617b cannot be used. ras ( o ) ras outputs row address strobe signal for sdram that is used as a video memory controlled by ygv627. since ras is always driven by ygv627, vram halt function of ygv617b cannot be used. cas ( o ) cas outputs column address strobe signal for sdram that is used as a video memory controlled by ygv627. since cas is always driven by ygv627, vram halt function of ygv617b cannot be used. we ( o ) we outputs write strobe signal for sdram that is used as a video memory controlled by ygv627. since we is always driven by ygv627, vram halt function of ygv617b cannot be used. dqmh, dqml ( o ) these pins output data mask signal for sdram that is used as a video memory controlled by ygv627. dqmh is for vd15 ? vd8, and dqml is for vd7 ? vd0. cs ( o ) this pin outputs chip select signal for sdram that is used as a video memory controlled by ygv627. ygv627 requires connection to sdram because the device uses cs control for access to sdram for power saving purpose and against switching noise. sdclk ( o ) this pin outputs clock for sdram that is used as a video memory controlled by ygv627. every output signal connected to sdram is outputted synchronizing with the rising edge of this clock. the read data from sdram is latched in the ygv627 at the rising edge of this clock. the clock enable pin of sdram should always be used in enable state.
ygv627 8 vr64 ( i: pull up ) high level is inputted when the capacity of sdram that is used as a video memory controlled by ygv627 is 16m bits, or low level is inputted when the capacity is 64m bits. this signal determines the function of signal outputted from ba1, ba0, and va11?va0 pins. connect with the sdram as specified below. since this pin is for selection of a mode, always fix it to either level. + v r64 = ?h? (when connected with 16m bits sdram) ygv627 pins cs ras cas we ba1 ba0 va11 va10 va9 va8 va7 ? 0 sdram pins cs ras cas we a11 a10 a9 a8 a7 ? 0 + v r64 = ?l? (when connected with 64m bits sdram) ygv627 pins cs ras cas we ba1 ba0 va11 va10 va9 va8 va7 ? 0 sdram pins cs ras cas we a13 a12 a11 a10 a9 a8 a7 ? 0 < display monitor interface> r, g, b ( o: analog output ) these pins output linear rgb signal. when a termination resistor of 37.5 ? is connected, voltage amplitude with resolution of 8 bits (256 levels) is outputted. these pins can directly drive a monitor whose impedance is 75 ? as shown below. r(g,b) r l =75 ? ? iref ( i: analog input ) reference current for rgb dac is inputted to this pin. the reference current of ? 9.38 ma provides amplitude of 0.7 vp-p (typical value). when supplying the refere nce current, use a current sink circuit as shown below. for the following circuit, adjust the values of r1 and r2 so that the pin potential of iref (v iref ) become approximately 1.37 v. iref (current sink circuit) r1 r1 r2 csync ( o ) this pin outputs a composite sync signal to external monitor. in interlace mode, it outputs equivalent pulse. vsync ( o ) this pin outputs vertical sync signal to external monitor. hsync ( o ) this pin outputs horizontal sync signal to external monitor. blank ( o ) this pin outputs a signal that indicates non-display period (blank period). therefore, it can be used as a signal that indicates valid display period for lcd panel.
ygv627 9 fsc ( o ) this pin outputs sub-carrier clock for video encoder. this pin can output a clock inputted to dtckin pin divided by 1, 2, 4 or 8 which may be selected in accordance with the register setting. inputting a clock of 14.318 mhz into dtckin pin provides sub-carrier clock of 3.58 mhz when divided by 4. dotclk ( o ) output signal of display data (analog r, g, b, dv17 ? dv0, ys, at) is outputted synchronizing with dotclk. dvout ( i: pull up ) this pin selects input/output of external video data terminal. the external video terminal becomes output when low level is inputted to this pin, or input when high level is inputted to this pin. the input/output of the external video data terminal can be changed with internal register exio(r#05). in such case, input high level to dvout or keep it open. dv17 ? 0 ( i/o: pull up ) these are input/output pins for digital external video data. these pins become input when high level is inputted to dvout and exio(r#05) =?0? is set, or becomes output when low level is inputted to dvout pin or exio(r#05) =?1? is set. for the external video data, a format with 6 bits for digital rgb individually, or a format with 6 bits for crycb individually can be selected. the format of the input / output data is as shown below. dv17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ( cr ) 5 ? 0 ( i/o ) g ( y ) 5 ? 0 ( i/o ) b ( cb ) 5 ? 0 ( i/o ) ys ( o ) when performing superimposition, this pin outputs a signal that controls switching with external signal. when displaying bitmap plane, this pin outputs inversion signal for ysn bits that can be set by dot. in the border displaying period or blank period, this pin outputs inversion signal of border ys data. at ( o ) this pin outputs 1 bit attribute data that can be set by display dot. when ate(r#05) signal of internal register is set to ?0?, the value set in the atd bit of register is outputted regardless the display data. when ?1? is set for ate signal, b0 (lsb of blue) that is inputted to dac for blue is outputted from at pin. at this time, the same data of msb is inputted to lsb of dac for blue. during the blank period, b0 of border is outputted when ate signal is set to ?1?. when the signal is set to ?1?, the value set to atd bit is outputted. this signal can be used, for example, for specifying semi-transparency (ym) when externally mixing display data. vsin ( i: pull up ) this signal resets the vertical timing of crt controller block of ygv627. when this input signal is sampled with period equal to the pulse width of horizontal sync signal , and low level is detected three times consecutively, the internal v counter is set at the first htl timing (horizontal sync signal start timing) immediately after the moment. in interlace mode, field identification is performed at the resetting of vertical timing by inputting composite sync signal of external video through this pin. this feature allows the superimposition synchronizing with frame period easily. if this signal is inputted during the display period, the display data of the next one field is not guaranteed. this pin can be kept open if this function is not used. the function of this pin is the same as that of v reset pin of ygv617b. sampling clock vsin htl timing v-counter ? counter set horizontal sync pulse width
ygv627 10 hsin ( i: pull up ) this signal resets the horizontal timing of crt controller block of ygv627. the horizontal timing is set to the horizontal sync starting position at the moment this signal falls from high level to low level, and at the same time, the phase of dot clock is reset. when the built-in pll is operated in the external sync mode, the input signal and output of hsync pin are locked. if this signal is inputted during the display period, the display data of the next line is not guaranteed. this pin can be kept open if this function is not used. the function of this pin is the same as that of hreset pin of ygv617b. < clocks> syckin ( i ) , syckout ( o ) crystal is connected to these pins to generate reference clock that is used in the system. the built-in pll produces sdram clock based on this clock. when supplying system clock and dot clock using the same clock through sysel pin (when low level is inputted to sysel), input the common clock through dtckin pin. at this time, input low level or high level signal into syckin pin. syckout pin can be kept open. when inputting externally generated clock, input it into syckin pin. syckin and syckout pins are the same as vckin and vckout pins of ygv617b. syckin syckout spllvssr, spllrref, spllfilt ( analog ) these pins are used to connect external resistors and capacitors for the built-in pll that produces sdram clock. for the details of resistors and condensers value in the following figure, please refer to the application manual. spllfilt spllrref spllvssr notes: 1. arrange the components so that the parasitic capacitance among spllfilt, spllrref and spllvssr is minimized and the signals do not cross each other. 2. pll may not lock if there is a time difference between the rising moment of avdd (for pll) and the rising moment of vdd (for digital logic).
ygv627 11 sysel ( i: pull up ) this signal selects the source of reference clock to be used in the system. when low level is inputted to sysel, the system clock and dot clock use the same source of the clock. in this case, the common clock is inputted into dtckin. therefore, there is no need to input clock into syckin. when high level is inputted to sysel, syckin pin input is used as the reference system clock independent from the dot clock. when sysel is used with low level input, be sure to input stable clock into dtckin even if the clock produced by the built-in pll is used as the dot clock. since sysel is used for selection of a mode, always fix it to either level. this pin has a pull-up resistor. the function of this pin is the same as that of vcks pin of ygv617b. dtckin ( i ) , dtckout ( o ) crystal is connected to these pins to input dot clock. when operating the built-in pll in fsc sync mode, the reference clock is inputted to these pins. at this time, the clock with multiple of fsc is to be inputted. when pll function is not used, this input clock is supplied directly to the crtc block and displays data control block. when low level is inputted to sysel, it is also supplied as the reference system clock. when inputted externally generated clock, input it into dtckin. dtckin and dtckout are the same as dckin and dckout of ygv617b. dtckin dtckout dpllvssr, dpllrref, dpllfilt ( analog ) these pins are used to connect external resistors and capacitors for the built-in pll that produces dot clock. when directly using dtckin input signal as dot clock without using the built-in pll, keep dpllfilt open and short-circuit between dpllrref and dpllvssr. for the details of resistors and condensers value in the following figure, please refer to the application manual. dpllfilt dpllrref dpllvssr notes: 1. arrange the components so that the parasitic capacitance among dpllfilt, dpllrref and dpllvssr is minimized and the signals do not cross each other. 2. pll may not lock if there is a time difference between the rising moment of avdd (for pll) and the rising moment of vdd (for digital logic).
ygv627 12 test2-0 ( i: pull up ) these pins are used for testing internal circuit of ygv627. be sure to keep them open (without connecting any component) when using the device. avdd1, avss1 ( i ) these pins supply power to vco analog circuit that generates sdram clock. connect +3.3 v to avdd1 and ground level to avss1. avdd2, avss2 ( i ) these pins supply power to vco analog circuit that generates dot clock. connect +3.3 v to avdd2 and ground level to avss2. avdd3, avss3 ( i ) these pins supply power to analog circuit of rgb dac section. connect +3.3 v to avdd3 and ground level to avss3. vdd, vss ( i ) these pins supply power to digital circuit of ygv627. connect +3.3 v to vdd and ground level to vss. ygv627 has several vdd and vss, all of which require power supply. connect a bypass capacitor between vdd and vss as a noise killer as close as possible to the pins. power supplies, vdd, avdd1, avdd2 and avdd3 are to be turned on at the same time, in principle. turning on the power supplies at the same time means that they are to be turned on before the potential difference between them reaches and exceeds 0.6 v. avoid making the potential difference 0.6 v or over continuously (over approximately one second), or the reliability of this lsi may be deteriorated. if the pot ential difference among the power supplies cannot be avoided, be sure to turn on/off vdd, avdd1, avdd2 and avdd3 so that their voltages do not exceed vdd.
ygv627 13 electrical characteristics absolute maximum ratings items symbol ratings unit supply voltage (vdd, avdd) v dd *1 ? 0.5 to +4.6 v input pin voltage (dtckin, syckin, vd15 ? 0) v i *1 ? 0.5 to v dd +0.5 v input pin voltage ( other than the above ) v i *1 ? 0.5 to 5.5 v output pin voltage v o *1 ? 0.5 to v dd +0.5 v output pin current i o ? 20 to +20 ma storage temperature t stg ? 50 to +125 c *1 : value with respect to vss (gnd) = 0v recommended operating conditions items symbol min. typ. max. unit supply voltage (vdd, avdd) v dd *1 3.0 3.3 3.6 v supply voltage v ss 0 v low level input voltage (vd15 ? 0) v il *1 ? 0.3 0.8 v high level input voltage (vd15 ? 0) v ih *1 2.2 v dd +0.3 v low level input voltage (dtckin, syckin) v il *1 ? 0.3 0.3v dd v high level input voltage (dtckin, syckin) v ih *1 0.7v dd v dd +0.3 v low level input voltage ( reset pin ) v il *1 ? 0.3 0.8 v high level input voltage ( reset pin ) v ih *1 2.4 5.3 v low level input voltage (other than the above) v il *1 ? 0.3 0.8 v high level input voltage (other than the above) v ih *1 2.2 5.3 v ambient operating temperature t op ? 40 +85 c *1 : value with respect to v ss (gnd) = 0v electrical characteristics under recommended operating conditions z dc characteristics items symbol min. typ. max. unit low level output voltage v ol *1 0.4 v high level output voltage *2 v oh *3 2.4 v input leakage current i li 10 a output leakage current i lo 25 a current consumption *4 *5 i dd 180 220 ma *1 : measurement condition i ol =1.6ma *2 : except open drain pin *3 : measurement condition i oh = ? 1.0ma *4 : typical value means average value obtained when a general image is displayed. *5 : maximum value means instantaneous maximum value obtai ned when the internal circuit is fully operated. z pin capacity items symbol min. typ. max. unit input pin capacity c i 8 pf output pin capacity c o 10 pf input / output pin capacity c io 12 pf
ygv627 14 z ac characteristics note: when measuring timing, the input signal reference level is 1.4 v and transition time tt=1 ns. the transition time is measured at the time of v ih and v il . when the transition time is over 1 ns, the input signal reference level is v ih (minimum value) and v il (maximum value). z clock input no. items symbol min. typ. max. unit dtckin : input clock frequency f dtck 1 14.32 *1 40 *2 mhz 1 dtckin : clock cycle time t dck 25 1000 2 dtckin : clock high level pulse width twh dck 11.25 3 dtckin : clock low level pulse width twl dck 11.25 ns dtckin : clock duty d dck 45 50 55 % syckin : input clock frequency f sck 1 16.6 33.3 mhz 1 syckin : clock cycle time t sck 30 1000 2 syckin : clock high level pulse width twh sck 13.5 3 syckin : clock low level pulse width twl sck 13.5 ns syckin : clock duty d sck 45 50 55 % *1 : this is the case of ntsc. use of other scanning mode allows optional selection of 13.5 mhz, 27 mhz, 28.6 mhz, 33 mhz or other frequency. *2 : when oscillating clock directly with xtal, the maximu m frequency is 33.3 mhz. when inputting clock over 33.3 mhz, input clock signal oscillated externally with clock module or other means into dtckin pin. 1.4v 1 23
ygv627 15 z reset input no. items symbol min. typ. max. unit 1 sdclk stabilization time after vdd input * 1 1 ms 2 sdclk signal stabilization time after syckin 1 ms 3 reset input pulse width tw rs 1.5 ms * 2 since ygv627 produces sdram clock with pll, it requires approximately 1ms after stabilization of power supply level and syckin pin input clock for stabilization of clock. moreover, in power on sequence of sdram, nop state *3 of 100 s to 500 s or over is needed after stabilization of the power supply level and clock frequency. keep these times with assert time of reset pin (low level pulse width twrs). after negating reset signal, power on sequence of sdram is started by issuing precharge all command (pall). power(vdd) reset syckin sdclk sdram nop 1 nop time start power on sequence 2 3 *1 : this rule applies from the moment all power supplies, vdd pin, avdd1 pin, avdd2 pin, and avdd3 pin are turned on. * 2 : the value when stabilization time of sdram is 500 s *3 : for the time needed for nop state, confirm the specification of sdram to be adopted.
ygv627 16 z system interface (measurement condition: c l =50 p f) no. items symbol min. typ. max. unit note 1 csreg , csmem setup time ts cs 2 2 csreg , csmem hold time th cs 0 3 a22 ? 0 setup time ts a 5 4 a22 ? 0 hold time th a 0 5 wr1-0 pulse width (@no wait access) tw lwr 20 7 6 d15 ? 0 setup time (@write access) ts d 10 7 d15 ? 0 hold time (@write access) th d 3 8 rd pulse width (@no wait access) tw lrd 2t sck +15 1 9 d15 ? 0 turn on time (@read access) ton d 0 15 10 d15 ? 0 turn off time (@read access) toff d 5 15 11 d15 ? 0 valid data output delay time (@read access) td d 0 12 ready , wait turn on time (z to h) ton rw 0 5 13 ready , wait delay time from wr1-0 active (h to l) td rw 45 6 14 ready hold time from wr1-0, rd inactive (l to h) th rewr 3 18 15 ready hold time from csreg , csmem inactive th recs 3 18 16 ready turn off time after csreg , csmem inactive toff rc 7 18 17 wait turn off time after csreg , csmem inactive toff wc 5 18 wr1-0, rd hold time after ready active or wait inactive th wr 0 19 wr1-0, rd ?high? level width after write access twh wrw 10 2 19 wr1-0, rd ?high? level width after write access twh wrw 2.5t s ck +15 3 19 wr1-0, rd ?high? level width after write access twh wrw 5.5t s ck +15 4 20 wr1-0, rd ?high? level width after read access twh wrr 10 21 dreq hold time th drq 0 22 dack pulse width tw ldak 20 23 dack high level width (@ 8bits system bus (lwd= ?0?)) twh dak 10 5 24 dack cycle time (@ 8bits system bus (lwd= ?0?)) tcy dak 2t sck 5 25 d15 ? 0 setup time (@dma access) ts dma 10 26 d15 ? 0 hold time (@dma access) th dma 10 27 dack delay time after cs inactive td dak 5 28 csreg , csmem delay time after dack inactive th cak 5 ns note 1 : defined with time from the fall of rd to the time settled read data is outputted. actually, it is necessary to keep setup time for the rise of rd . note 2 : when hardware wait is permitted note 3 : after write access to other than r#00-0e when hardware wait is prohibited (no wait mode) note 4 : after write access to r#00-0e when hardware wait is prohibited (no wait mode) note 5 : valid only when system bus is 8 bits (low level is inputted to lwd pin) note 6 : value at the time when sufficient time elapses from write access immediately before note 7 : conditions of both tw lwr 20ns and tw lwr td rw must be met when wait and read y are used.
ygv627 17 z write cycle ( wr1-0 control) csreg csmem a 22-0 wr1-0 d15-0 read y wait 1 3 2 4 valid data 5 6 7 12 13 12 13 18 18 14 15 16 17 z read cycle ( rd control) csreg csmem a 22-0 rd d15-0 ready wait 1 3 2 4 valid data 9 12 12 13 11 11 18 18 14 15 16 17 10 8 z wr1-0 , rd input prohibited period csreg csmem wr1-0 rd 19 19 20 20 z dma access dreq dack d15-0 csreg csmem write data write data 21 22 22 23 25 26 25 26 27 28 24
ygv627 18 z sdram interface (measurement condition c l = 3 0 p f) no. items symbol min. typ. max. unit note 1 sdclk:cycle time tcsdclk 15 1,2 2 sdclk:clock jitter - 1 1 3 sdclk:clock width twsdclk 5 1 4 vd[15:0]:input data setup time tsvd 2 1 5 vd[15:0]:input data hold time thvd 2 1 6 output signal:hold time th sdo 2 3 7 output signal:delay time td sdo 12 ns 3 note 1: pll must be in stabilized state. note 2: sdclk is oscillated with built-in vco. oscillated frequency range of vco ranges from 110 mhz to 134 mhz. therefore, the frequency range of sdclk must be set for 55 mhz through 66.6 mhz. note 3: output signals are those outputted from the following pins. ba1 ? 0, va11 ? 0, vd15 ? 0, cs , ras , cas , we , dqmh, or dqml sdclk vd[15:0] (input ) output signals 1 4 5 6 7 33
ygv627 19 z monitor interface (measurement condition c l = 3 0 p f) no. items symbol min. typ. max. unit note 1 dotclk:delay time td dotclk 15 1 2 csync , vsync , hsync , dv17 ? 0 (out) :output hold time thdisp 0 3 csync , vsync , hsync , dv17 ? 0 (out) :output delay time td disp 15 4 fsc:delay time td fsc 15 5 hsin , vsin ,dv17 ? 0 (in) :input setup time tssin 10 6 hsin , vsin ,dv17 ? 0 (in) :input hold time th sin 5 ns note 1: when pll is not used (r#22:dcks= ?0?) dtckin dotclk outputs fsc inputs 1 3 2 1 1 4 5 6
ygv627 20 z characteristics of rgb output pins items symbol min. typ. max. unit resolution 8 bit settling time r l =37.5 ? 24 ns output hold time c l =30pf 5 ns amplitude of output voltage iref= ? 9.38ma 0.7 v deviation of vp-p of r, g and b 3 % settling time is defined as the period from the rise of dotclk to the time when output level of dac enters in the range of 1/2 lsb of the dotclk level after changing. output hold time is defined as the period from the rise of dotclk to the time when output level of dac goes out of the range of 1/2 lsb of the dotclk level after changing. dotclk r g b settling time hold time 1/2 lsb 1/2 lsb r,g,b measurement circuit rl cl
ygv627 21 example of system configuration 3 ygv627(avdp3e) rgb d15-0 vd15-0 ba1-0 va11-0 a22-0 spllfilt spllrref spllvssr syckout syckin cpu 16 16mbit to 64mbit x 16bit 12 8 or 16 23 or 22 monitor sdram csync dtckin vsin hsin dv17-0 18 dvout external video equipment dot clock vsync hsync digital rgb iref (current sink circuit) (lcd or crt etc.)
ygv627 22 external dimensions of package
ygv627 23
ygv627 24 the specifications of this product are subject to improvement changes without prior notice. notice

▲Up To Search▲

Price & Availability of YGV627-V

	To Download YGV627-V Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .